A circuit designer may code a finite state machine implemented with elements, such as latches and flip-flops, in a Hardware Definition Language (HDL), such as the Very High Speed Integrated Circuits Hardware Definition Language (VHDL) (defined as IEEE Standard 1076/2002). The code defining the circuit design, also known as the design specification, may then be subject to register transfer level (RTL) synthesis and retiming to reposition latches and flip-flops to optimize the design while preserving the input-output behavior of the circuit defined in the HDL code. The synthesis of the HDL code translates the logical description of the circuit defined by the HDL code into a network of standard cells that satisfies a set of timing constraints. The synthesized result comprises a retimed implementation of a netlist of digital cells, having technology specific digital cells required for the design.
After the synthesis and optimization operation, a verification operation is performed to verify the original design specification with the retimed implementation, i.e., the netlist implementation. Certain verification processes, such as those based on reachability analysis, are computationally expensive, and the computational cost of verification increases as the number of sequential elements, e.g., flop-flops, latches, etc., in the design increases.